ROBERT PRIMAS

I work as a Research Scientist at Intel Labs. Before that, I completed a Ph.D. in Computer Science at Graz University of Technology. My research interests include practical and theoretical aspects of information security. On the practical side, I work on designing and attacking implementations of (post-quantum) cryptography in hardware/software that come with protection mechanisms against physical attacks such as power/fault analysis. On the more theoretical side, I work on designing and analyzing cryptographic modes that provide high resistance against physical attacks or the formal verification of algorithmic countermeasures against physical attacks. I am a co-author of ISAP, a lightweight authenticated encryption scheme that gives strong guarantees against various kinds of physical attacks. ISAP reached the final round of the NIST standardization process for lightweight cryptography.

• Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs (pdf)
• Power Contracts: Provably Complete Power Leakage Models for Processors (pdf)
• Statistical Ineffective Fault Attacks on Masked AES with Fault Countermeasures (pdf)
• Protecting against Statistical Ineffective Fault Attacks (pdf)
• Chosen Ciphertext k-Trace Attacks on Masked CCA2 Secure Kyber (pdf)

• 2023/06/21: Efficient Second-Order Masked Software Implementations of Ascon in Theory and Practice
  @ NIST Lightweight Cryptography Workshop 2023
• 2023/02/10: Side-Channel and Fault Analysis of Cryptographic Implementations
  @ Graz University of Technology

At Graz University of Technology, I taught a master-level course focusing on implementing and attacking cryptographic implementations for four years. The hardware part of this course covers amongst others power analysis attacks, fault attacks, and corresponding countermeasure techniques. Students receive real hardware for conducting these tasks.

• Side-Channel Security (current course overview)

• Optimized (protected) software implementations of Ascon (git) and ISAP (git)
• A Fast and Compact Accelerator for Ascon and Friends (git)
• Hardware reference implementations of Ascon (git, git) and ISAP (git)
• Hardware design of Ascon with protection against power analysis (git)
• Formal masking verification tool Coco (git) with (secured) Coco-IBEX core (git)

• CHES: 2025
• CASCADE: 2025
• FDTC: 2019, 2020, 2021, 2022, 2023

• 2024: CHES
• 2023: CHES, CRYPTO, CT-RSA
• 2022: CHES, SAC
• 2021: ASIACRYPT, CHES, COSADE, SAC
• 2020: CHES, CRYPTO, EUROCRYPT
• 2019: AFRICACRYPT, CHES
• 2018: AFRICACRYPT, CHES, EuroS&P

• ACM Computing Surveys (CSUR)
• The Computer Journal (COMJNL)
• Microprocessors and Microsystems: Embedded Hardware Design (MICPRO)
• Cryptography and Communications Discrete Structures, Boolean Functions and Sequences (CCDS)
• IEEE Transactions on Computers (TC)
• IEEE Transactions on Information Forensics & Security (TIFS)
• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)